Recently, a cross point-type semiconductor memory device (referred to as the “cross point memory” occasionally hereinafter) comprising a memory cell array in which a memory cell is not provided with a selection element other than a memory element, and the memory element is directly connected to a data line (row selection line) and a bit line (column selection line) in the memory cell has been developed (refer to the following Non-patent document 1 and Patent document 1, for example).
According to the cross point memory, the memory cell is so constituted that a variable resistance element is positioned at a cross point of the data line and bit line of the memory cell array and one of a lower electrode and an upper electrode of each variable resistance element is connected to the data line and the other is connected to the bit line. For example, the following Non-patent document 1 discloses a variable resistance-type nonvolatile memory (TF-RRAM) in which a chalcogenide material is used and a resistance value is changed by applying an electric pulse to a memory cell.
The following Non-patent document 1 proposes a ½ bias method and a ⅓ bias method as a method of applying a programming voltage to a data line and a bit line, at the time of a programming action in a predetermined memory cell in a memory cell array. FIG. 20 shows voltage applied states of the data line and the bit line in the ½ bias method, and FIG. 21 shows voltage applied states of the data line and the bit line in the ⅓ bias method.
As shown in FIG. 20, according to the ½ bias method, in order to perform programming by changing resistance by applying a bias voltage to a variable resistance element of the selected memory cell enclosed with a circle (the memory cell enclosed with a circle in the figure), a first programming voltage (Vw, for example) and a second programming voltage (0V, for example) are applied to a selected data line and a selected bit line connected to the selected memory cell, respectively. At this time, a middle voltage Vw/2 that is the half of the programming voltage Vw is applied to non-selected data lines and non-selected bit lines which are not connected to the selected memory cell so that the programming voltage Vw (=Vw−0V) is not applied to non-selected memory cells which are not to be programmed. That is, in order to prevent the non-selected memory cells that are not to be programmed from being programmed, the low middle voltage that is not enough for the programming is positively applied to the non-selected memory cells connected to the selected data line and the selected bit line. Therefore, according to the ½ bias method, since the middle voltage (the half of the programming voltage Vw) is applied to both the non-selected memory cells connected to the selected data line and the non-selected memory cells connected to the selected bit line (the memory cells enclosed with rhombuses in the figure), a bias current is generated and the problem is that programming current is increased.
As shown in FIG. 21, according to the 113 bias method, in order to perform programming by changing resistance by applying a bias voltage to a variable resistance element of the selected memory cell enclosed with a circle (the memory cell enclosed with a circle in the figure), a first programming voltage (Vw, for example) and a second programming voltage (0V, for example) are applied to a selected data line and a selected bit line connected to the selected memory cell, respectively. At this time, a voltage Vw/3 that is one third of the programming voltage Vw is applied to non-selected data lines not connected to the selected memory cell and a voltage 2Vw/3 that is two thirds of the programming voltage Vw is applied to non-selected bit lines not connected to the selected memory cell, so that the programming voltage Vw (=Vw−0V) is not applied to non-selected memory cells which are not to be programmed. That is, in order to prevent the non-selected memory cells that are not to be programmed from being programmed, a bias voltage (|Vw/3|) that is not enough for the programming is positively applied to all the non-selected memory cells so that the programming voltage is not directly applied to the non-selected memory cells. Therefore, according to the ⅓ bias method, since the low bias voltage (one third of the programming voltage Vw) is applied to both the non-selected memory cells connected to the selected data line and the non-selected memory cells connected to the selected bit line (the memory cells enclosed with rhombuses in the figure) and remaining all the non-selected memory cells connected to the non-selected data lines or the non-selected bit lines, a bias current is generated in all the non-selected memory cells, and the problem is that programming current is increased. In addition, according to the ⅓ bias method, although the bias voltage applied to each non-selected memory cell is lower than that in the ½ bias method, since the number of non-selected memory cells receiving the bias voltage is greatly increased, the programming current is considerably increased.
In addition, the following Patent document 1 proposes a memory cell array constitution suitable for high concentration of memory cells of a MRAM (Magnetic Random Access Memory). In addition, the MRAM is a nonvolatile memory device using a tunneling magnetoresistive (referred to as the TMR hereinafter), whose programming method is different from that in the variable resistance-type nonvolatile memory disclosed in the Non-patent document 1. FIG. 22 shows a main circuit constitution proposed in the Patent document 1.
As shown in FIG. 22, according to the circuit constitution of the MRAM disclosed in the Patent document 1, a memory cell array MA has a plurality of TMR elements 12 arranged in an X direction (row direction) and a Y direction (column direction) in the shape of an array. In the X direction, j pieces of TMR elements 12 are arranged and in the Y direction (4×n) pieces of TMR elements 12 are arranged.
The four TMR elements 12 arranged in the Y direction constitute one reading block BKik (i=1 to j, k=1 to n). One row is provided by j pieces of reading blocks BKik arranged in the X direction. The memory cell array MA has n rows. In addition, one column is provided by n pieces of reading blocks BKik arranged in the Y direction. The memory cell array MA has j columns. First ends of the four TMR elements 12 in the block BKik are commonly connected, for example, connected to a source line SLi (i=1 . . . j) through a reading selection switch RSW1 configured by a MOS transistor. The source line SLi extends in the Y direction and only one is provided in one column, for example. The source line SLi is connected to a ground point Vss through a column selection switch CSW configured by a MOS transistor, for example.
In this circuit constitution, the memory array in which j pieces of reading blocks BK11 constituted by the four TMR elements 4 are arranged in the X direction and one reading block BK11 is arranged in the Y direction is called a bank (basic cell array block). Bank selection transistors RSW2 and RSW1 for selecting the bank are provided on the row side and the column side, respectively. In addition, the memory array in FIG. 22 comprises n pieces of banks arranged in the Y direction.
Meanwhile, since the memory cell shown in FIG. 22 is the TMR element of the MRAM, a current does not flow in the TMR element of the memory cell at the time of a programming action, so that a current does not flow in the bank selection transistors RSW2 and RSW1. At the time of reading action, a current flowing in the TMR element of the memory cell that is proportional to the resistance value of this element is detected to determine 1 or 0. Therefore, only at the time of reading action, a small current flows through the bank selection transistors. That is, since a large current required for the programming action does not flow in the bank selection transistors, and the bank selection transistors supply only the small current at the time of reading action, the size of the bank selection transistors is relatively small.
However, in the variable resistance-type nonvolatile memory in which change in resistance value is detected by applying an electric pulse to a metal oxide containing transition metal oxide such as Pr1-xCaxMnO3(PCMO), NiO2,TiO2, HfO2, and ZrO2 having a perovskite structure, a current flows in the memory cell also at the time of programming action. Therefore, it is necessary to supply a current required for the programming action to a bank to be programmed through the bank selection transistor. Since the current required for the programming action is larger than that flowing at the time of reading action, the size of the bank selection transistor is larger than that of the bank selection transistor required in the MRAM.
FIG. 23 shows a circuit constitution of a cross point-type memory cell array including a variable resistance element formed of a metal oxide such as PCMO in a memory cell. In FIG. 23, peripheral circuits such as a row decoder and a column decoder are not shown and only a memory cell array and a transistor for controlling the memory cell array are shown. In addition, the number of variable resistance elements in the basic memory array corresponding to the reading bank BK11 in FIG. 22 is eight and the memory cell array is provided by arranging the 128 basic memory arrays in the row direction and one in the Y direction to constitute one bank (basic memory cell array bank) in FIG. 23. Bank selection transistors RBS0 to 7 (not shown) for selecting the bank are provided on the side of the row and bank selection transistors CBS0 to 127 (not shown) are provided on the side of the column. In addition, FIG. 23 shows the memory cell array in which only one bank is provided in the Y direction.
FIG. 23 shows current flows with solid line arrows and broken line arrows when the programming action is performed in six selected memory cells connected to a bit line BL2 to be programmed and enclosed with circles, at the same time. In addition, the six selected memory cells are provided at the cross points of data lines DL0, 1, 2, 4, 5, and 7 and the bit line BL2, and the broken line arrow shows a bias current flowing in non-selected memory cells on the data line DL0. The programming method is the above ½ bias method in which the programming voltage Vw is applied to the selected data lines DL0, 1, 2, 4, 5, and 7, 0V is applied to the selected bit line BL2, and the middle voltage Vw/2 that is the half of the programming voltage Vw is applied to the non-selected data lines DL3 and 6, and the non-selected bit lines BL0, 1, 3 to 127.
A current IR0 flowing in the bank selection transistor RBS0 connected to the data line DL0 is calculated. It is assumed that a programming current of about 75 μA is generated in the selected memory cells. In addition, since the bias voltage of Vw/2 is applied to each of the other 127 non-selected memory cells connected to the data line DL0, a bias current Ibias0 is generated. This bias current Ibias0 is expressed by the following equation (1) and the current IR0 is expressed by the following equation (2). Here, it is assumed that the bias voltage Vw/2 is 2V, each resistance value R of the non-selected memory cells is a low resistance value of 50 kΩ.Ibias0=Vw/(2×R)×127=2[V]/50[kΩ]×127=5.08 [mA]  (1)IR0=0.075 [mA]+Ibias0=5.155 [mA]  (2)
In a case where a data width of the variable resistance-type nonvolatile memory is eight bits and one bit is stored in each memory cell, when the programming action is performed for the six memory cells of the eight memory cells connected to the bit line BL2 shown in FIG. 23 at the same time, since a current having the same current value as the IR0 flows in the bank selection transistors RBS0, 1, 2, 4, 5 and 7 at the same time, its total current value IW is expressed by the following equation (3), so that it can be seen that the current at the time of programming action is increased.IW=5.155×6=30.9 [mA]  (3)
As described above, when the programming method proposed in the Non-patent document 1 is used in the variable resistance-type nonvolatile memory having a variable resistance element whose resistance value is changed by electric pulse application and which is formed of PCMO having a perovskite structure, metal oxide containing transition metal oxide such as NiO2, TiO2, HfO2 and ZrO2, or a chalcogenide compound, such as an OUM (ovonic memory), the current at the time of programming action is increased.
Since the fact that there are many non-selected memory cells connected to the selected data line causes the current at the time of programming action to be increased, it is considered that the number of columns constituting one bank is reduced from 128 to 32, for example. When one bank has a constitution of 8 rows×32 columns, a bias current Ibias0′ per selected data line, a current IR0′ flowing in the bank selection transistor RBS0 and a total current value IW′ are considerably reduced as shown in the following equations (4) to (6).Ibias0′=Vw/(2×R)×31=2[V]/50 [kΩ]×31=1.24 [mA]  (4)IR0′=0.075 [mA]+Ibias0′=1.315 [mA]  (5)IW′=1.315×6=7.89 [mA]  (6)
FIG. 24 shows a case where four banks each having a memory cell array constitution of 8 rows×32 columns are provided in the row direction without layering data lines (FIG. 24A), and a case where one bank having a constitution of 8 rows×128 columns in the row direction (FIG. 24B) to schematically compare their layout occupied areas. In addition, in FIGS. 24A and 24B, peripheral circuits (peripheral circuits 1, 2) such as a driver for driving the data line and a row address decoder are arranged on both sides of each bank.
As shown in FIG. 24, when four independent banks constitute the memory array of 8 rows×128 columns (FIG. 24A), the current at the time of the programming action can be reduced, but the layout area of the peripheral circuits is increased as compared with the case of the one-bank constitution (FIG. 24B), so that the ratio in the whole memory cell array is increased and the chip size is increased.    Patent document 1: Japanese Laid-Open Patent Publication No. 2003-249629    Non-patent document 1: Y Chen et al., “An Access-Transistor-Free (0T/1R) Non-Volatile Resistance Random Access Memory (RRAM) Using a Novel Threshold Switching, Self-Rectifying Chalcogenide Device”, IEDM Technical Digest, Session 37.4, 2003